接口时序对数字中频发射机边带抑制的影响  

Effect of Interface Timing Belt on the Digital Intermediate Frequency Transmitter

作　　者：郑秀云[1] 

机构地区：[1]中兴通讯股份有限公司RRU开发部,上海201203

出　　处：《电子科技》2013年第7期119-121,124,共4页Electronic Science and Technology

摘　　要：结合AD9142在GSM无线通信发射机中的应用,指出了边带信号对系统性能的影响,着重从原理上分析了接口时序错误对边带信号的贡献、成因及改善方法,并给出了时序优化前后的数据对比验证结果。为了保证DAC输出性能达到最优,需要保证接口时序满足建立时间和保持时间要求。通过调整基带处理侧的延时和DAC内部的延时可以使接口时序满足要求。With the AD9142 GSM wireless communication transmitter applications as examples, this article discusses the impact of sideband signals on system performance with emphasis on the theoretical analysis of the causes of interface timing errors and their contribution to the sideband signal. Improvement methods are proposed and a comparison of data before and after timing optimization is given. In order to ensure optimal performance of the DAC output, the interface timing must meet the setup and hold time requirements, which can be achieved by adjusting the baseband side of the delay.

关 键 词：复调制 DAC 正交调制 AD9142 时序 

分 类 号：TN911.2[电子电信—通信与信息系统]