A 0.9-V switched-opamp-based delta-sigma ADC with dual cycle shift DWA  被引量:2

A 0.9-V switched-opamp-based delta-sigma ADC with dual cycle shift DWA

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作  者:赵津晨 赵梦恋 吴晓波 王汉卿 

机构地区:[1]Institute of VLSI Design,Zhejiang University

出  处:《Journal of Semiconductors》2013年第6期110-117,共8页半导体学报(英文版)

基  金:supported by the National Natural Science Foundation of China(No.60906012)

摘  要:This paper presents a low-power high-precision switched-opamp(SO)-based delta-sigma(△Σ) analog-to -digital converter(ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit(FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.This paper presents a low-power high-precision switched-opamp(SO)-based delta-sigma(△Σ) analog-to -digital converter(ADC).The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit(FOM) of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.

关 键 词:analog-to-digital converter delta-sigma modulation low-voltage low-power analog circuit SWITCHED-OPAMP 

分 类 号:TN722.77[电子电信—电路与系统]

 

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