基于VerilogHDL的异步串行通信IP核设计  

IP Core Design of Asynchronous Serial Communication Based on VerilogHDL

作　　者：李健[1] 吕胜涛[2] 

机构地区：[1]中国兵器工业第五八研究所军品部,四川绵阳621000 [2]中国人民武装警察部队装备研究所,北京100012

出　　处：《兵工自动化》2013年第7期86-88,共3页Ordnance Industry Automation

摘　　要：为提高CPU的工作效率,设计基于VerilogHDL的异步串行通信IP核。阐述了异步串行通信的原理、NiosII嵌入式处理器的系统架构和Avalon总线特性,分析了异步串行通信的实现方法,给出了各功能模块的接口关系,并设计完成可供Sopc Builder直接调用的串行通信IP核,能正确实现异步串行数据收发功能。实践结果证明:该设计不但实现了异步串口的正常通信,而且使用方便、通信效率高。For improving CPU work efficiency, asynchronous serial communication IP core based on VerilogHDL is designed. Introduce asynchronous serial communication principle, Nios II embedded processor system structure and Avalon bus feature, analyze realization method of asynchronous serial communication, put forwards interface relation of each function module. Designed and achieved the IP core of serial communication, it can be used easily by Sopc Builder and can correctly execute the function of receive and transmit of asynchronous serial data. The example proved that the design not only realize the correct communication of serial port, but also can be used convenient and get a better communication.

关 键 词：串行通信 VERILOGHDL IP核 

分 类 号：TJ02[兵器科学与技术—兵器发射理论与技术]