基于窗结构和巴切奇偶排序的中值滤波器硬件设计与实现  

Hardware design of the median filter based on window structure and batcher′s odd-even sort network

作　　者：孙凯旻[1] 王亮[1] 顾美康[1] 

机构地区：[1]上海师范大学信息与机电工程学院,上海200234

出　　处：《上海师范大学学报（自然科学版）》2013年第3期271-276,共6页Journal of Shanghai Normal University(Natural Sciences)

摘　　要：数字电路设计中值滤波器时,面积和速度上的考虑非常重要.面积上要求使用的逻辑资源尽可能少;速度上则要求系统能在较高时钟频率上工作,并用尽可能少的时钟周期完成1帧滤波或进行实时滤波.设计的新型中值滤波器的硬件结构为带2个Buffer的3窗结构,并用奇偶排序网络作为滤波器功能逻辑模块的理论依据,在FPGA平台上进行结构设计,使用ModelSim仿真验证了结果,最后实现了视频图像滤波.实验分析表明,设计的新型结构滤波器不但使用的逻辑资源较少,仅用了741个逻辑单元(LE),而且处理速度达到27 MHz/像素,实现了对视频图像的30帧/s实时处理.设计不仅具有一定的实用性,也为数字图像处理的硬件结构设计思路提供了参考.Area and speed are two important factors to be considered in designing Median Filter with digital circuits. Area consid- eration requires the use of logical resources as little as possible,while speed consideration requires the system capable of working on higher clock frequencies, with as few clock cycles as possible to complete a frame filtering or real time filtering. This paper gives a new design of Median Filter,the hardware structure of which is a 3 x 3 window structure with two buffers. The filter func- tion module is based on Batcher＇s Odd-Even Sort network theory. Structural design is implemented in FPGA, verified by ModelSim software and realizes video image filtering. The experimental analysis shows that this new structure of Median Filter effectively de- creases logical resources （merely using 741 Logic Elements） , and accelerates the pixel processing speed up to 27MHz. This filter achieves real-time processing of video images of 30 frames/s. This design not only has a certain practicality, but also provides a reference for the hardware structure design ideas in digital image processing.

关 键 词：中值滤波器 FPGA 数字图像处理 奇偶排序网络 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]