基于VLSI平台的AVR处理器仿真与设计  

Simulation and design of AVR processor based on VLSI platform

作　　者：张益男[1] 何菁[1] 袁杰[2] 

机构地区：[1]南京大学金陵学院信息科学与工程学院,江苏南京210089 [2]南京大学电子科学与工程学院,江苏南京210093

出　　处：《现代电子技术》2013年第14期127-130,共4页Modern Electronics Technique

基　　金：江苏省自然科学基金(2010386)

摘　　要：传统的微处理器由于内部有限的逻辑资源和外部固定的引脚封装,大大限制了应用范围。为此,在阐述微控制器的内部结构、存储器管理结构和指令集结构后,利用现场可编程门阵列丰富的逻辑资源,虚拟出传统微控制器的处理器核心,添加Wishbone总线,将处理器核心与通用外设连接构成一个虚拟的微控制器平台,并使用硬件描述语言Verilog和VHDL,自底向上设计AVR处理器核心,与通用外设互连组成系统,使用XILINX VirtexⅡPro芯片进行板级验证。结果表明,实现了既定目标,与标准的微控制器兼容,系统运行稳定。该方法延续了传统微控制器的生命力,能使其得到更大发展。Internal limited logic resources and external fixed-pin package of traditional microprocessors greatly limit their application range. The internal structure, memory management structure and instruction set architecture of micro control unit （MCU） are described. The abundant logic resources of field programmable gate array （FPGA） are used to virtualize the proces-sor core of traditional MCU. Wishbone bus is added to connect processor core with common peripherals to form a virtual MCU platform. Moreover, the bottom-up design of AVR core is performed with hardware description languages such as Verilog and VHDL, which is connected with common peripherals to build a system. Board level validation was carried out with XILINX Vir-tex-Ⅱ Pro chip. The result shows that the set objective is achieved and the system which runs stable is compatible with standard MCU. This method continues the vitality of traditional MCU, and makes it further progressed.

关 键 词：微控制器 哈佛结构 现场可编程门阵列 WISHBONE总线 

分 类 号：TN911-34[电子电信—通信与信息系统] TP338[电子电信—信息与通信工程]