分组密码算法SM4的低复杂度实现  

Low Complexity Implementation of Block Cipher SM4 Algorithm

作　　者：王晨光[1] 乔树山[1] 黑勇[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《计算机工程》2013年第7期177-180,共4页Computer Engineering

基　　金："核高基"重大专项"基于可编程逻辑阵列IP的SoC设计"(2009ZX01034-002-004-007(002))

摘　　要：针对分组密码算法SM4中加解密算法与密钥扩展算法的相似性,提出一种将加解密模块与密钥扩展模块复用的基本架构,通过对具体实现结构的分析与选择,使控制逻辑复杂度、复用模块复杂度以及系统吞吐量之间得到权衡。基于该架构设计SM4加解密IP核,在现场可编程门阵列上占用的资源仅为传统设计的55%,基于SMIC 0.18μm数字CMOS工艺的综合结果显示,仅用0.079 mm2即可实现100 Mb/s的数据吞吐量。实验结果表明,该结构可以有效地降低SM4算法的实现复杂度。A basic architecture is proposed for reducing the implementation complexity of SM4 block cipher. The architecture reuses the hardware of encryption/decryption and key expansion module because the encryption/decryption algorithm is very similar with the key expansion algorithm. Optimum trade-off among control-logic complexity, reused-module complexity and throughput is realized through careful analysis and choose of specific realization. A SM4 cipher IP is designed based on this architecture. The designed IP＇s cost is only 55% of the traditional design in Field Programmable Gate Array（FPGA）. The IP is also synthesized under the SMIC 0.18 μm CMOS process. Its area is 0.079 mm^2 with 100 Mb/s throughput. Experimental results of synthesis show that the proposed architecture can reduce the implementation complexity of SM4 block cipher efficiently.

关 键 词：SM4算法 分组密码算法 低复杂度 硬件复用 现场可编程门阵列 特定用途集成电路实现 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]