宽函数的布尔匹配及其在FPGA重综合中的应用  

Boolean Matching of Wide Functions and Its Application to Resynthesis of FPGA

作　　者：张峰[1] 王作建 吴洋 于芳[1] 刘忠立[1] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]北京飘石科技有限公司,北京100029

出　　处：《华南理工大学学报（自然科学版）》2013年第5期34-42,共9页Journal of South China University of Technology(Natural Science Edition)

基　　金：武器装备预研基金资助项目(110***110***02098)

摘　　要：当前大多数商用现场可编程门阵列(FPGA)可配置逻辑块结构在查找表(LUT)的基础上增加了很多辅助逻辑资源,而传统的LUT基工艺映射算法无法充分利用这些资源.为此,文中提出一种基于香农展开式和不相交支持集分解算法的布尔匹配方法,并将其应用于工艺映射后的重综合.使用该方法对工艺映射后网表中的宽函数进行布尔匹配,使其在目标FPGA结构上重新实现,从而达到充分利用所有逻辑资源和减少LUT数的目的.实验结果表明,该方法能在不增加电路关键路径延时的基础上,对学术界综合工具ABC工艺映射之后的4-LUT和6-LUT网表分别节省7.9%和7.8%的面积开销.The configurable logic block （CLB） of the existing commercial FPGAs （Field Programmable Gate Arrays） comprises not only lookup table （LUT） but also many assistant logic resources that cannot be fully utilized by the conventional LUT-based mapping algorithms. In order to solve this problem, a Boolean matching method for post-mapping resynthesis is proposed based on the Shannon expansion and the DSD （ Disjoint Support Decomposition） algorithm. This method helps to implement the Boolean matching of wide functions of mapped LUTs and reimplement the wide functions with target FPGA CLB, so as to make full use of all logic resources in CLB and reduce the number of LUTs. From the mapped results generated by state-of-the-art FPGA mapper ABC, it is found that the proposed method reduces the number of LUTs respectively by 7.9% for 4-LUT networks and by 7.8% for 6-LUT networks while preserving the logic depth.

关 键 词：电子设计自动化 现场可编程门阵列 布尔匹配 宽函数 重综合 可配置逻辑块 查找表 

分 类 号：TN47[电子电信—微电子学与固体电子学] TP319[自动化与计算机技术—计算机软件与理论]