高速高精度模数转换器的数字后台校准算法  

Digital Background Calibration Algorithm for High-Speed and High-Resolution Analog-Digital Converter

作　　者：熊召新[1] 蔡敏[1] 贺小勇[1] 

机构地区：[1]华南理工大学电子与信息学院,广东广州510640

出　　处：《华南理工大学学报（自然科学版）》2013年第6期17-22,共6页Journal of South China University of Technology(Natural Science Edition)

基　　金：国家"863"计划项目(2009AA01Z260)

摘　　要：研究了模数转换器(ADC)的数字后台校准技术,提出了一种针对2.5 b/级高速高精度流水线ADC的数字后台校准算法.在2.5b/级电容翻转式余量增益电路(MDAC)中注入与输入信号相关的抖动信号,提取MDAC中由于电容失配和放大器增益有限性造成的非线性误差,并在最终的数字输出端对这些误差进行校准.文中提出的数字后台校准算法具有电路实现简单、不中断ADC正常工作、适合高速高精度流水线ADC等优点,能有效地降低电容失配和放大器有限增益等非理想因素对流水线ADC精度的影响.仿真结果表明,经校准后的ADC信号噪声失真比可从63.3dB提高到78.7dB,无杂散动态范围由63.9 dB提高到91.8 dB.This paper deals with the digital background calibration technique of analog-to-digital converter（ADC） and presents a new algorithm applied to the high-speed and high-resolution 2.5-b / stage pipelined ADC.In this algorithm,signal-dependent dither signals are injected into the 2.5-b / stage flip-over multiplying DAC（MDAC） to measure the nonlinear errors resulting from capacitor mismatch and finite opamp gain in MDAC and feed back the errors to the digital outputs of pipelined ADC for correction.This calibration algorithm is easy to realize and can works at very high speed without interrupting the normal operation of high-resolution ADC.Moreover,it can effectively calibrate all gain errors resulting from capacitor mismatch,finite opamp gain and other sources.Behavior simulation results show that,by using the proposed calibration scheme,the signal-to-noise distortion ratio increases from 63.3dB to 78.7 dB and the spurious-free dynamic range improves from 63.9 dB to 91.8 dB.

关 键 词：流水线模数转换器 校准 抖动信号 电容失配 放大器 有限增益 

分 类 号：TN47[电子电信—微电子学与固体电子学]