基于BiCMOS的高性能CML三值D型触发器的设计  

Design of high-performance CML ternary D flip-flop based on BiCMOS

作　　者：赵祥红[1,2] 沈继忠[2] 

机构地区：[1]浙江大学宁波理工学院信息科学与工程学院,浙江宁波315100 [2]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《山东大学学报（工学版）》2013年第3期99-104,共6页Journal of Shandong University（Engineering Science）

基　　金：国家自然科学基金资助项目(61071062);宁波市自然科学基金资助项目(2011A610109)

摘　　要：结合电流模逻辑(current-mode logic,CML)电路的高速低摆幅、抗干扰能力强、适合在高频下工作的优点以及BiCMOS电路高速大驱动的优点,设计了一种结构简单的基于BiCMOS的高性能CML三值D型触发器。采用TSMC 180 nm工艺,使用HSPICE进行模拟。结果表明,所设计的触发器不仅具有正确的逻辑功能,且结构简单,与目前先进的三值D型触发器相比,平均D-Q延时降低95.6%～98.4%,PDP降低16.2%～96.8%,同时工作频率可高达15 GHz,适合高速和高工作频率的应用。A simple-structure high-performance CML ternary D flip-flop based on BiCMOS was proposed, which com-bined both advantages of BiCMOS and CML circuits, and included high-speed and strong drive ability of BiCMOS circuits and high speed low swing and low noise of CML circuits. Using TSMC 180 nm process, the results of simula-tions carried out by HSPICE illustrated that the proposed circuit could not only have correct logic function, but also gain improvements of 95.6%-98.4% in average D-Q delay and 16. 2%-96. 8% in PDP compared with the advanced ternary D flip-flops. Furthermore, the work frequency could perform up to 15 GHz. All of the results proved that the proposed circuit was suitable for high-speed and high-frequency applications.

关 键 词：触发器 多值逻辑 电流模逻辑 低功耗 高速集成电路 

分 类 号：TN43[电子电信—微电子学与固体电子学] TN46