总线事务级验证模型仿真性能研究  

HDL modeling and Performance Evaluation for Bus Function Model

作　　者：周萌[1] 刘恺[1] 高松涛[1] 邱善勤[1] 

机构地区：[1]工业和信息化部软件与集成电路促进中心

出　　处：《中国集成电路》2013年第8期23-27,51,共6页China lntegrated Circuit

摘　　要：系统芯片的功能验证一直是芯片设计中最具挑战性的部分。基于事务的验证方法学被用来解决功能验证中的困难。该方法学通过提高验证的抽象层次来降低验证复杂度。但同时也对使用该方法学构建的验证平台组件可重用性有了更高的要求。其中总线功能模型可以在验证中模拟设计中的其他模块,是构建验证平台的重要组件。本文在方法学的基础上,讨论了两种类型的总线功能模型,并给出了verilog硬件描述语言的实现模型,最后通过实验比较了两种总线功能模型的仿真性能。SoC Design Function Verification is consistently one of the most difficult challenging aspects of design. A transaction-based verification methodology （ TVM ） has being developed to present some particular challenges by raising the verification effort to a higher level of abstraction. At the same time, this methodology requests the reusability of each component in the lest benches. Bus Function Model can be used to emulate other blocks in the design, and BFM is a important module types for building the test bench based on TVM. The paper discussed two types of BFM, then the verilog implement model of each type is given in this paper, finally the reusability and performance of both types are compared through experiments.

关 键 词：功能验证总线功能模型事务验证平台 

分 类 号：TN47[电子电信—微电子学与固体电子学]