基于FPGA的AVS帧内预测电路设计  

FPGA-based design of intra mode prediction in AVS video encoder

作　　者：李文军[1] 王祖强[1] 徐辉[1] 张贞雷[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2013年第8期50-53,共4页Application of Electronic Technique

摘　　要：提出了一种AVS高清视频编码器帧内预测模块硬件结构。通过对AVS帧内预测各个预测模式的分析,设计了帧内预测编码流水线结构和模式预测运算单元电路。根据各预测模式的编码运算关系,合理安排流水线结构,采用8 bit数据并行流水处理,实现了高清视频帧内预测实时编码。将除Plane模式之外的其他预测模式采用同一硬件电路来实现,对运算比较复杂的Plane模式单独设计了硬件结构,节省了硬件资源。In this paper, a hardware architecture of AVS HD intra predictor is proposed. After the analysis of each prediction mode, a pipeline of the intra prediction encoder and the hardware of processing element are designed. According to the relationship of each prediction mode, the pipeline is reasonable organized. The encoder can encode 8 pixels in one cycle and realize the HD video sequences real-time encoding. All of the prediction modes but Plane mode are implied in the same hardware circuit and the Plane mode is implied in a different hardware, which saves the hardware resources. The design improves the usage of the hardware.

关 键 词：AVS 帧内预测 硬件架构 流水线 并行处理 

分 类 号：TN919.8[电子电信—通信与信息系统]