多微通道内存系统设计方法  

Design of multiple micro-channel memory systems

作　　者：张广飞[1,2,3] 王焕东[1] 陈新科[1,2,3] 黄帅[1] 陈李维[1,2,3] 

机构地区：[1]中国科学院计算机系统结构重点实验室,北京100190 [2]中国科学院计算技术研究所,北京100190 [3]中国科学院研究生院,北京100049

出　　处：《高技术通讯》2013年第7期685-693,共9页Chinese High Technology Letters

基　　金：国家"核高基"科技重大专项课题(2009ZX01028-002-003;2009ZX01029-001-003);国家自然科学基金(60921002;61003064)资助项目

摘　　要：通过建立内存系统排队模型,分析了影响内存系统性能的原因——内存控制器的内存命令处理速度受访存请求页命中率、Bank级并行度和读写命令切换率的影响,进而提出了一种多微通道内存系统设计方法。用此方法多微通道内存控制器通过对内存颗粒进行细粒度控制,可以提高访存请求页命中率和Bank级并行度,隐藏数据总线读写切换延迟。该结构在提高内存系统带宽利用率的同时,缩短访存请求延迟,并提高内存功耗有效性。将多微通道内存控制器设计应用于多核处理器平台,充分分析各种宽度访存通道对应用程序性能的影响。实验结果表明,相比传统内存控制器设计方法,多微通道内存控制器将内存系统带宽提高了21.8%,访存延迟和功耗分别降低14.4%和26.2%。to the queuing theory, a memory system pertormance model was established, and the key tactors aI fecting the memory controller and then the performance of the memory system were analyzed. Further, a method for design of multiple microchannel memory systems （MMCM） was proposed. The design can bring the advantages below. By controlling DRAM devices concurrently, multiple banks can be opened simultaneously, which decreases bank conflicts and promotes DRAM data bus utilization. All the channels share the same DRAM command bus in sequence. The DRAM operation power is reduced to a large extent since fewer DRAM devices are involved in every DRAM command. Different data streams corresponding to different DRAM commands can flow from or to DRAM devices concurrently. The memory queuing latency can be reduced. MMCM systems can achieve the best perform ance/power efficiency. The experimental results show that, compared with conventional desgins MMCM can im prove the memory system bandwidth by 21.8%, and decrease the memory access latency by 14.4% with 26.2% reduction in DRAM power consumption on average.

关 键 词：DRAM系统 内存控制器 片上多核 多通道 访存特性 

分 类 号：TP333.1[自动化与计算机技术—计算机系统结构]