基于CPLD的光电编码器的四倍频计数电路设计  

Fourfold Frequency Multiplication Counter Circuit Design of Photoelectrical Encoder Based on CPLD

作　　者：郭键[1] 朱杰[1] 

机构地区：[1]北京物资学院信息学院,北京101149

出　　处：《计算机测量与控制》2013年第7期1878-1879,1888,共3页Computer Measurement &Control

基　　金：北京市教育委员会科技计划面上项目(KM201310037001);北京市属高等学校人才强教计划资助项目(PHR201108311);2010年北京市优秀人才培养资助项目(2010D005009000002)

摘　　要：分析光电编码器四倍频原理,基于可编程逻辑器件CPLD对光电编码器输出信号进行倍频、鉴相、计数;光电编码器的输出信号对于CPLD内部电路而言是异步信号,CPLD采用两级触发器构成的同步器对编码器输出的AB相信号进行同步,大大降低了亚稳态对编码器计数的影响;该设计应用在某型号便携式检测仪器中,其采用500线分辨力的编码器,实现了0.1mm定位精度;实验结果表明该设计计数准确可靠,硬件电路简化,提高了被控对象的测量精度和控制精度。The principle of fourfold frequency multiplication of photoelectrical encoder is analyzed in this article. And a method based on Complex Programmable logic device （CPLD） to multiply the output signal of the photoelectrical encoder, differentiates its phase and counts its number is put forward. The output signal of photoelectrieal encoder is asynchronous for CPLD internal circuit and the synchronizer formed by two flip--flops are used to synchronize the encoder＇s AB phase output signal, which greatly reduces the influence on encoder counts from metastable status. When the encoder with 500 counts per revolution resolution is used in some portable testing instruments, 0. lmm positio- ning accuracy can be obtained. The experimental result shows that the count is accurate and reliable, the hardware circuit is simple, which

关 键 词：CPLD 光电编码器 四倍频 亚稳态 同步器 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]