多发射多流水线结构数字信号处理器设计  

Design of a 32-Bit Digital Signal Processor with Multi-Issue and Multi-Pipeline Architecture

作　　者：陈超[1] 张盛兵[1] 

机构地区：[1]西北工业大学计算机学院,陕西西安710072

出　　处：《西北工业大学学报》2013年第3期422-428,共7页Journal of Northwestern Polytechnical University

基　　金：国家自然科学基金(61173047;61003037);高等学校博士点专项科研基金(20116102120049)资助

摘　　要：zw100处理器是西北工业大学和某研究所共同研制的采用MCU-DSP相融合架构的32位数字信号处理器。提出一种多发射多流水线结构来进行数字信号处理器的微体系结构设计,使该处理器同时具备了RISC load/store体系结构、DSP的计算能力和MCU的实时控制能力等特点。从zw100处理器指令集设计出发,首先介绍了该处理器架构和主要单元,然后重点讨论了基于多发射多流水线结构的指令调度策略、相邻指令耦合关系与发射机制、多发射条件下流水线相关的处理等。最后,对设计进行了仿真验证,并给出综合结果。目前,该处理器已采用TSMC 65nm CMOS工艺流片成功,频率达到500 MHz,达到2G MAC/s的运算能力,性能指标满足设计要求。A 32-bit digital signal processor（DSP）,which is based on MCU-DSP architecture is presented.A smart micro-architecture is proposed with the distinguishing features of multi-issue and multi-pipeline.It helps DSP chip make a balance among low power,high performance digital signal process and real-time response.The key point of the architecture is that the dynamical instruction dispatching scans the dependence relationship between two or among three adjacent instructions in the instruction queue and then decides the way of instruction issue.If the instructions are distributed in some special way,the fetch instruction unit is allowed to dispatch three instructions into three independent pipelines in parallel at the same time,otherwise they must to dispatch in sequence.Subsection 3.1 of the full paper describes how we verify the design of our zw100 DSP chip and subsection 3.2 describes how we analyze its logic synthesis capability.The DSP chip is fabricated with TSMC 65nm CMOS technology;the core frequency is 500 MHz and operational capability attains 2G MAC/s.

关 键 词：数字信号处理器 多发射 多流水线 MCU-DSP架构 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]