Low leakage 3×VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process  

作　　者：YANG ZhaoNian LIU HongXia WANG ShuLong 

机构地区：[1]Key Laboratory of Wide Bandgap Semiconductor Materials and Devices of Ministry of Educ13ation,School of Microelectronics,Xidian University

出　　处：《Science China(Technological Sciences)》2013年第8期2046-2051,共6页中国科学（技术科学英文版）

基　　金：supported by the National Natural Science Foundation of China (Grant Nos. 61076097,60936005);in part by Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program (Grant No. 20110203110012)

摘　　要：A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.

关 键 词：detection circuit electrostatic discharge（ESD） leakage current over-stress voltage stacked-transistors 

分 类 号：TN386.1[电子电信—物理电子学]