基于邻行链接访问的低功耗指令高速缓存  

Low power instruction cache based on adjacent line linking access

作　　者：项晓燕[1] 陈志坚[1] 孟建熠[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2013年第7期1213-1217,共5页Journal of Zhejiang University：Engineering Science

基　　金：中央高校基本科研业务费资助项目(2012QNA5004)

摘　　要：通过分析高速缓存访问的局部性原理,提出当前高速缓存访问行与若干紧邻行链接访问的低功耗指令缓存访问方法.该方法能够在发生相对跳转时依托于相邻行之间的访问链接信息,精确获得跳转目标行的路访问信息,减少对高速缓存标志存储器的访问,达到降低动态功耗的目的.在高速缓存行发生替换时,仅需检测并清除被替换行相邻范围内的若干缓存行的链接信息,从而实现链接关系的正确性.与基于路记忆访问的高速缓存器相比,应用该方法的高速缓存器的动态功耗可以平均减少6%.The behavior of cache accessing was analyzed. A new low power instruction cache accessing method that links the current cache line and its adjacent cache lines was proposed. When a direct jump be- tween cache lines occurs, the adjacent cache line links are reused to get the accurate way information of the target line. Then the accesses of tag array are reduced and tag lookups are avoided to reduce the dynamic power consumption. When a cache line is evicted, only its adjacent cache line links should be checked and invalidated to keep the correctness of the links. Experiment results show that dynamic power consumption can be reduced by 6 % on average with the new method compared to the traditional way memorization in- struction cache.

关 键 词：指令高速缓存 低功耗 邻行链接访问 

分 类 号：TN332[电子电信—物理电子学] TN47