低电源电压超低功耗Delta-Sigma调制器  

Low voltage ultra-low power delta-sigma modulator

作　　者：赵津晨[1] 赵梦恋[1] 吴晓波[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2013年第7期1225-1231,共7页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(60906012);浙江省自然科学基金资助项目(LY13F040001)

摘　　要：为了在低电源电压约束下实现delta-sigma模数转换器(ADC)的低功耗与高精度设计,提出基于开关型运放以及新颖DWA技术的delta-sigma调制器.其中的开关型运放仅工作于半周期相位,可以在低于1V的电源电压下正常工作,节省了系统功耗.调制器的积分器采用运放分享技术,以降低硬件开销.采用双向循环移位数据加权平均(DCS-DWA)技术,在抑制调制回路中匹配单元误差引起的非线性失真的同时消除了与输入信号相关的寄生音调,提高系统分辨率.提出的delta-sigma调制器在SMIC 0.18μm 1P6M工艺下流片,动态范围与峰值SNDR分别达94.6和92.5dB,芯片面积为0.72mm2.在0.9V电源电压下,测得系统功耗仅为56μW,品质因数(FoM)低至34.2fJ/c-step.结果表明,预期的主要设计目标均已实现.A switched-opamp （SO） based delta-sigma modulator with novel data weighted averaging （DWA） technique was presented in order to achieve a high resolution low power consumption delta-sigma analog-to-digital converter （ADC） under the constraint of low supply voltage. The proposed SO structure operated only during a half clock phase under a sub-1 V supply voltage, which effectively reduced the pow- er consumption of the system. The opamp-shared technique was applied to save the hardware overhead. Due to the use of dual cycle shift data weighted averaging （DCS-DWA） technique, the nonlinear distortion caused by units mismatch in the feedback loop of the modulator was removed without introducing signal- dependent tones, so that the resolution of the system could be improved. The proposed delta-sigma modu- lator was implemented in a SMIC 0.18 μm 1P6M process. The measured dynamic range and peak signal to noise and distortion ratio （SNDR） were 94. 6 dB and 92.5 dB, respectively, and the core area of the modu- lator was 0. 72 mm2. The total power consumption was 56 μW when a 0.9 V supply voltage was provided, and the figure-of-merit （FoM） was only34.2 fJ/c-step. The measurement results showed that the expec- ted specifications were achieved.

关 键 词：超低功耗设计 数据转换器 DELTA-SIGMA调制器 运算放大器(op-amp) 

分 类 号：TN453[电子电信—微电子学与固体电子学]