基于FPGA＋DSP的信号处理板多处理器加载设计  

Design of Multi-Processor Loading System Based on the FPGA and DSP Signal Processing Board

作　　者：高俊山[1] 芦山[1] 肖逍[1] 

机构地区：[1]哈尔滨理工大学自动化学院,黑龙江哈尔滨150080

出　　处：《控制工程期刊（中英文版）》2013年第4期282-287,共6页Scientific Journal of Control Engineering

摘　　要：水声信号处理系统，因需实时处理数据，处理数据量大等需求，多采用多处理器协同的结构。因其上电加载稳定性和配置加载数据存储方案的考虑，需对多处理器加载时序，方式进行设计。该文采取了一种基于FPGA＋DSP构架的多处理器加载方法。对系统上电加载时序，各处理器加载方式，加载代码的存储，数据流向等方面进行了设计。实现FPGA，DSP的动态配置和加载，提高了系统稳定性，省去FPGA等处理器专用配置FLASH芯片，分利用了系统资源。Underwater acoustic signal processing system mostly adopts multi-processor structures due to its requirement for real-time data processing and large amount of data processing. The way of the multi-processor loads and time series are carefully designed concerning the loading stability and configuration of loading data storage while power is on. This paper describes a multi- processor loading method based on FPGA associated with DSP architecture to deal with system＇s electrified sequence loading, loading method of each processor, storage of loaded code, data flow mode and other aspects. Dynamic configuration on FPGA and DSP has been realized, and the system stability is enhanced. It also omits configuration of specific FLASH chip under the application of FPGA or other processors by coordinating system resources.

关 键 词：多处理器 加载 FPGA DSP 内存循环复用 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]