Dynamic Power Dissipation Control Method for Real-Time Processors Based on Hardware Multithreading  

硬件多线程处理器的动态功耗控制方法(英文)

作　　者：罗新强 齐悦 王磊 王沁 

机构地区：[1]School of Computer and Communication Engineering, University of Science and Technology Beijing [2]Beijing Key Laboratory of Knowledge Engineering for Materials Science [3]Institute of Automation, Chinese Academy of Sciences

出　　处：《China Communications》2013年第5期156-166,共11页中国通信（英文版）

基　　金：supported partially by the National High Technical Research and Development Program of China (863 Program) under Grants No. 2011AA040101, No. 2008AA01Z134;the National Natural Science Foundation of China under Grants No. 61003251, No. 61172049, No. 61173150;the Doctoral Fund of Ministry of Education of China under Grant No. 20100006110015;Beijing Municipal Natural Science Foundation under Grant No. Z111100054011078;the 2012 Ladder Plan Project of Beijing Key Laboratory of Knowledge Engineering for Materials Science under Grant No. Z121101002812005

摘　　要：In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

关 键 词：dynamic power dissipation control  real-time processor  hardware multithread low power design  energy efficiency 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TN432[自动化与计算机技术—计算机科学与技术]