一种PON结构航空总线协议芯片的内存架构  

The Memory Architecture of PON Structure Avionic Bus Protocol Chip

作　　者：周鹏飞[1] 宗竹林[1] 肖龙[1] 

机构地区：[1]电子科技大学电子科学技术研究院,四川成都611731

出　　处：《微电子学与计算机》2013年第9期5-8,共4页Microelectronics & Computer

基　　金：航空科学基金(20090580013;20110580002);中央高校基础研究基金(ZYGX2009J092)

摘　　要：在分析了基于PON结构的FC-AE总线的基础上,以提高系统传输效率、降低总线功耗为目的,提出了一种使用基于共享存储器和循环存储的数据存储,采取双缓存任务执行机制和内存动态访问控制机制的内存访问方式.软硬件协同测试结果表明,该内存架构具有任务执行效率高,系统交互时间少和动态功耗低的特点.In order to improve the efficiency of the data storage and reduce bus power consumption, a kind of memory architecture with the characteristics of shared storage, circular storage, and global double buffering mechanism has been presented, which is based on the analyses of transmission characteristics of FC--AE bus rely on PON structure. The experimental results show that this architecture has merits of high reliable performance, low delay time and low power dissipation, by testing the co--verification platform with the hardware and software.

关 键 词：无源光网络 光纤通道 航电总线 低功耗 

分 类 号：TN402[电子电信—微电子学与固体电子学]