一种基于FPGA的抽取滤波器的实现与优化  

An Implementation of Decimation Filter Based on FPGA

作　　者：王亚磊[1] 张浩[1] 杨亚光[1] 陈立平[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2013年第9期119-121,125,共4页Microelectronics & Computer

摘　　要：提出一种在FPGA中以CIC抽取滤波器及CIC补偿滤波器实现的抽取滤波结构.该结构以时间换空间的设计思想实现,最大可能的减少了硬核乘法器数量.同时结合FPGA资源分布特点,提出了以嵌入式RAM单元为核心的实现方法,极大减少了逻辑单元消耗,优化了资源分配,以最合理的资源消耗,实现了很高的滤波性能.This paper proposes a decimation filter structure, which is implemented in FPGA with CIC decimation filter and CIC compensation filter. This structure is based on the idea of trading time for space. It has greatly reduced the number of hard-- nucleus multipliers. Besides, it takes advantage of the characteristics of FPGA＇ s resource distribution, and has proposed a way to use embedded RAM. It has reduced the cost of logic elements and optimized the allocation of resources. Good filtering performance has been got with the most reasonable cost of

关 键 词：抽取滤波 FPGA 乘累加 嵌入式RAM 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]