FPGA中网络通信协议栈的裁剪及其全硬件实现  

Design and full hardware implementation of simplifed network communication protocol stack in FPGA

作　　者：蒋沪生[1] 柴志雷[1] 钟传杰[1] 

机构地区：[1]江南大学物联网学院轻工过程先进控制教育部重点实验室,江苏无锡214122

出　　处：《计算机工程与设计》2013年第9期3074-3077,3083,共5页Computer Engineering and Design

基　　金：国家自然科学基金项目(60703106)

摘　　要：针对基于FPGA的嵌入式系统中软件网络协议栈需要内置CPU的不足,阐述了采用全硬件方式实现网络协议栈的必要性,并提出了适合的网络通信协议栈裁剪方案。该协议栈包含精简的UDP、IP、以及MAC层驱动,可完成常规的网络通信。协议栈完全采用硬件描述语言编写,并在FPGA中实现。实验结果表明,该协议栈只占用2K逻辑资源,能以100Mbps的速率在FPGA与PC之间进行数据传输,为基于FPGA的系统调试及运行提供了一种简易的高速通信手段。Traditional network protocol stack by software need to use an embedded CPU core. Aiming at the insufficient of that, the necessary of design and implementation the network protocol stack is expounded using hardware, an network protocol stack simplify method is presented, this simplified stack on a FPGA system is implemented. The protocol stack includes UDP andIP and the MAC layer. Protocol stack is descripted totally by hardware description language and is implemented in FP- GA. Testing results indicate that the data transmition is stable and reliable and the network transmition speed can reach 100Mbps. This hardware protocol stack provides a high speed communication method in system debugging and running based on FPGA.

关 键 词：网络通信 硬件协议栈 UDP IP协议 现场可编程门阵列 硬件实现 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]