AVS编码器中帧内预测模块的硬件设计  

Hardware Design of Intra Prediction for AVS Encoder

作　　者：黄圣勋[1] 王法翔[1] 钟昌标[1] 

机构地区：[1]福州大学物理与信息工程学院福建省集成电路设计中心,福建福州350002

出　　处：《电视技术》2013年第17期80-83,共4页Video Engineering

摘　　要：根据AVS标准中帧内预测算法的特点,提出了一种应用于AVS高清实时编码器的帧内预测硬件设计方案。该设计中将亮度和色度预测共用一个预测单元,采用6路数据并行流水处理的结构,提高了处理速度。同时在分析AVS帧内预测各模式算法的基础上,结合移位寄存器操作实现各模式运算单元的进一步资源共享,简化了参考数据选择机制,减少资源消耗。实验结果表明,该设计完全能够满足高清视频图像(1 920×1 080,30 f/s(帧/秒))实时编码要求。According to the algorithms of AVS intra prediction, a hardware architecture for real-time AVS HD video encoder is proposed in this paper. The luminance and chrominance prediction share a prediction unit in the design, and the parallel pipeline of six intra prediction data is used to improve the processing speed. Based on analyzing the algorithm of each mode of the AVS intra prediction, the design realizes the further resource sharing of public operation unit with shift register operation. It will simplified the reference data selection mechanism and reduce the consumption of resources. The experimental results show that the design could be used for real-time encoding of HD video（1 920× 1 080,30 f/s）.

关 键 词：AVS标准 视频编码 帧内预测 并行处理 

分 类 号：TN919.81[电子电信—通信与信息系统]