用于芯片测试的环路滤波器设计  

Design of Loop Filter Used in Chip Testing

作　　者：唐锐[1] 

机构地区：[1]工业和信息化部电子第五研究所,广东广州510610

出　　处：《电子产品可靠性与环境试验》2013年第4期81-84,共4页Electronic Product Reliability and Environmental Testing

摘　　要：小数分频频率合成器在测试时必须外接一个环路滤波器电路与压控振荡器才能构成一个完整的锁相环电路。其外围电路中环路滤波器的设计好坏将直接影响到芯片的性能测试。以ADF4153小数分频频率合成器为例,研究了其外围环路滤波器的设计方法,给出了基于芯片测试的环路滤波器设计流程,并进行了验证测试。测试结果表明,该滤波器可满足小数分频频率合成器芯片测试的需要。An external loop filter and VCO are necessary for fractional-N frequency synthesizer to form a complete phase locked loop. The quality of loop filter affects the performance of chip testing directly. Design method of the external loop fractionai-N frequency synthesizer ADF4153. Design on the chip testing is developed. Verification testing shows that loop filter can meet the need of fractional-N filter is studied on the example of flow of the external loop filter based is carried out. The performance test result frequency synthesizer chip testing.

关 键 词：小数分频频率合成器 环路滤波器设计 芯片测试 

分 类 号：TN713.4[电子电信—电路与系统]