一种新型高速宽带数字下变频器的FPGA实现  

A New High-speed Variable-bandwise Digital Down-converter Based on FPGA

作　　者：庞少龙[1] 马志刚[1] 吴子贤[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《电子科技》2013年第9期106-109,112,共5页Electronic Science and Technology

摘　　要：数字下变频器是软件无线电宽带数字接收机的核心组成部分,经典的数字下变频结构难以实现高速率的混频与滤波,因此针对软件无线电系统小型化和低功耗的要求,提出一种新型的宽带数字接收机中数字下变频器的设计与FPGA实现方法,该方法采用基于多相滤波正交化处理从而实现数字接收机。文中分析了其设计原理以及FPGA实现,测试结果表明,设计具有良好的可扩展性和灵活性。Digital Down-Converter is a key component of Variable-bandwise digital receiver. Since it is hard for the typical DDC structure to implement high operation rates of mixing and filtering, for the miniaturization and low power requirements of SDR （ Software Defined Radio） , a new method is proposed for implementing Digital Down-Converter in Variable-bandwise digital receiver based on FPGA. This method is based on orthogonal poly-phase filter processing. This paper analyzes the principle of its design and FPGA implementation, and finally gives the test re-sults, which shows that the design has good scalability and flexibility.

关 键 词：软件无线电 数字下变频 正交化 多相滤波 FPGA 

分 类 号：TN92[电子电信—通信与信息系统]