从低速存储器到高速FPGA配置的位流解压缩  

From Low Memory to the High-speed FPGA Configuration Bit Stream

作　　者：包朝伟 刘仕东[2] 王佩宁 

机构地区：[1]深圳市国微电子有限公司,深圳518057 [2]中兴通讯股份有限公司微电子研究院,深圳518005

出　　处：《科学技术与工程》2013年第24期7255-7261,共7页Science Technology and Engineering

摘　　要：如果配置FPGA的位流很大,存储位流的存储器就会需要更大的空间,同时配置时间也会很长。为了节约存储空间和提高配置速度,提出了一种解决途径,即在存储芯片(比如Flash存储器)内嵌一个解压缩结构。为了实现这个目标,讨论了两种压缩算法:PDLZW和LZSS。通过对这两种算法的改进,使其适合设计的要求:好的压缩比,解压缩器消耗硬件资源少和有较好的数据吞吐率。实验表明,提出的压缩和解压缩算法,不仅可以减少近30%的存储空间,还能提高将近一倍的数据输出速率。If a bitstream of configuration for FPGA is very large, larger memory space for bitsteam and the longer time of configuration for FPGA will be needed. In order to save storage space and improve the allocation rate, a solution is proposed, that is, memory chip （such as Flash memory） embedded in a decompression structure. To achieve this goal, two compression algorithms are discussed： PDLZW and LZSS. Hence these two algorithms to fit our requirement： a good compression ratio, consumes less hardware resources, better data throughput. Experiments show that not only can be reduced to 30% of storage space, but also improved the data output rate nearly double via proposed compression and decompression algorithms.

关 键 词：FPGA PDLZW算法 LZSS算法 压缩 解压缩 数据吞吐率 

分 类 号：TP393.02[自动化与计算机技术—计算机应用技术]