用于植入式医用芯片的低电压低功耗SAR ADC  

Low Voltage Low Power SAR ADC for Implantable Medical Chips

作　　者：刘旸[1] 秦琳[1] 赵梦恋[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《江南大学学报（自然科学版）》2013年第4期424-428,共5页Joural of Jiangnan University (Natural Science Edition)　

摘　　要：为适应植入式医用芯片的使用要求,给出一低电压低功耗逐次逼近型模数转换器(SARADC)的设计。从降低功耗出发,提出了一种新的能量高效开关策略。与传统开关策略相比,电容阵列的平均开关能量减少了68%,电容阵列的面积仅为传统开关策略的50%;采用带校正的动态比较器,在提高精度的同时可以降低功耗;采用异步时钟,省略了高频时钟产生器,进一步降低了功耗。提出的5 Ms-111位SAR ADC采用SMIC 0.18μm CMOS混合信号工艺流片。供电电压低至1 V,功耗仅为0.236 mW,SNDR,SFDR分别达到55.1,68.38 dB。核心面积为650μm×1 000μm,符合植入式系统的要求。This paper presents a successive approximation register （SAR） ADC for implantable medical chips and a novel energy efficient switching method for reducing power. Compared with the conventional method, the average switching energy for cap array is reduced by 68% and the area of capacitor array is reduced to just 50%. A dynamic comparator with calibration is adopted to improve accuracies and reduce power consumption. An asynchronous clock is adopted to avoid high frequency clock generator. The 5 Ms-1 11 bit SAR ADC is fabricated in SMIC 0.18 μm CMOS mixed signal process. The low supply voltage is 1 V. The proposed ADC method can achieves a SNDR of 55.1 dB, a SFDRof 68.38 dB and a power consumption of 0.236 mW. The core area is 650μm × 1 000 μm. This ADC core can be used in implantable chips.

关 键 词：植入式 逐次逼近型 模数转换器 低电压 低功耗 

分 类 号：TN453[电子电信—微电子学与固体电子学]