全数字锁相环中宽带数控振荡器设计  

Wideband Digitally Controlled Oscillator Design in ADPLL

作　　者：韩晖翔[1] 俞思辰[1] 闵昊[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2013年第4期505-511,516,共8页Journal of Fudan University：Natural Science

摘　　要：在TSMC 65nm工艺下设计了一个调谐范围为3～5GHz、用于全数字锁相环的宽带数控LC振荡器.该振荡器的电容阵列分成粗调、中调和细调三个阵列,其中粗调为MIM开关电容,中调和细调采用数控人造介质(DiCAD)实现.测试结果表明:当中心频率为3GHz和5GHz时,频偏1MHz处相位噪声分别为-123dBc/Hz和-116dBc/Hz,功耗分别为12mA和5mA.A wideband digitally-controlled LC oscillator used for all digital PLL is designed in TSMC 65 nm process. The varactor bank is divided into 3 banks, including coarse-tuning bank with MIM switchable capacitors, mi＆tuning bank and fine-tuning bank consisting of DiCAD. The phase noise is --123 dBc/Hz or --116 dBc/Hz at 1 MHz offset, and the power dissipation is 12 mA or 5 mA, when the central frequency is 3 GHz or 5 GHz, respectively.

关 键 词：数控振荡器 宽带 数控人造介质 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学]