用于高性能电流舵型DAC的数字校准模块  

A Digital Calibration for High-Resolution Current Steering DAC

作　　者：林宇婧[1] 程龙[1] 叶凡[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201303

出　　处：《复旦学报（自然科学版）》2013年第4期517-525,共9页Journal of Fudan University：Natural Science

基　　金：国家科技重大专项(2009ZX03007-002-02);上海市学科带头人计划(08XD14007)资助项目

摘　　要：提出了一种用于14-bit 400MS/s电流舵型数字模拟转换器的数字校准模块.在校准关闭时,该模块仅作为温度计译码器进行编码转换.在校准开启时,校准开关基于一个低频校准时钟,依次对电流单元进行校准.由于使用单一频率的校准时钟会在SFDR中引入杂散尖峰,降低DAC的动态性能,所以本设计中的数字校准时钟模块采用了LFSR与CA叠加的结构,在频带上提供近似白噪声的输出控制信号.该数字模块采用SMICCMOS 0.18μm 1P6M工艺,电源电压为1.8V.研究结果表明,在200MHz下,对5MHz的输入信号,模块开启后,SFDR的提升接近18dB.可知,该模块可以大幅提高数模转换器的SFDR,可用于高性能电流舵型DAC中.A digital calibration technique for 14-bit 400 MS/s current steering DAC is presented. Under calibration module, the block acts as thermo decoder, and generates a calibrated clock to control the switch array to calibrate each current source. Single frequency clock can cause a repeating pattern of errors that appears as spurious tones, leading to low performance. A random clock based on LFSR and CA is introduced to convert the spurs into noise. The circuit has been designed and implemented in SMIC 0. 18 ktm CMOS 1P6M process. The supply voltage is 1.8 V. The final results indicate that this calibration technique improves SFDR up to 18 dB for 5 MHz input signal at 200 MHz clock. This technique could improve SFDR and be used in high-resolution current steering DAC.

关 键 词：电流舵型数模转换器 LFSR CA 数字校准 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]