应用于全数字锁相环的动态器件匹配与低功耗鉴相技术  

Dynamic Element Matching and Low-Power Phase Detecting Technology Applied in ADPLL

作　　者：刘鹏飞[1] 李巍[1] 李宁[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2013年第4期526-534,共9页Journal of Fudan University：Natural Science

基　　金：国家自然科学基金(61176029);国家"十二五"预研课题(513***)资助项目

摘　　要：提出了应用于全数字锁相环的改进的动态器件匹配技术和低功耗鉴相技术.利用低功耗鉴相技术简化了传统的全数字锁相环的鉴相原理,发明出一种新型的数字鉴相器,降低了数字电路实现的复杂性,降低了功耗;同时,本文所述的应用于全数字锁相环的动态器件匹配技术,降低了电容的工艺偏差对锁相环输出调谐曲线的不利影响,优化了锁相环的性能.该全数字锁相环采用TSMC 0.13μm CMOS工艺进行设计,仿真结果表明,本文所述的低功耗鉴相器功能正确,可使全数字锁相环正确地锁定在2.4～5.2GHz,本文所述的基于改进算法的芯片中鉴相器部分具有传统架构鉴相器53.2%的功耗与66.5%的芯片面积.测试结果表明,动态器件匹配技术使振荡器的输出调谐曲线(本文指输出频率与DCO调制字码值的曲线关系)更加接近理想情况.Improved dynamic element matching and low-power phase detecting technology applied in all digital phase lock loop（ADPLL） are proposed. The lower-power phase detecting technique lowers the power consumption and circuit complexity in digital circuit by simplifying the traditional phase detecting principle and developing a new- type phase detector. Meanwhile, in order to weaken the influence of digital controlled oscillator（DCO） capacitor mismatch to loop output tuning curve, the dynamic element matching technology is applied in the all digital phase lock loop. The proposed phase lock loop is fabricated in TSMC 0. 13μm CMOS technology. Simulation results show that the low-power phase detector works correctly, cuts the power consumption to 53. 2%, and cuts area to 66.5% also, the locking range of the proposed phase lock loop is from 2.4 GHz to 5.2 GHz. The measurement results show that the tuning curve of DCO with DEM is far closer to the ideal tuning curve than that of I3（20 without DEM.

关 键 词：全数字锁相环 数字鉴相器 低功耗 动态器件匹配 调谐曲线优化 

分 类 号：TN432[电子电信—微电子学与固体电子学]