A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator  

作　　者：韩雪 樊华 魏琦 杨华中 

机构地区：[1]Division of Circuits and Systems,Department of Electronic Engineering,Tsinghua University

出　　处：《Journal of Semiconductors》2013年第8期120-126,共7页半导体学报（英文版）

基　　金：supported by the PhD Programs Foundation of the Ministry of Education of China(No.20111011315);the National Science and Technology Important Project of China(No.2010ZX03006-003-01)

摘　　要：This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.

关 键 词：analog to digital converter common-centroid symmetry layout successive approximation register time domain comparator 

分 类 号：TN792[电子电信—电路与系统]