A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter  

作　　者：李学清 樊华 魏琦 徐震 刘嘉男 杨华中 

机构地区：[1]Department of Electronic Engineering,Tsinghua National Laboratory for Information Science and Technology,Tsinghua University

出　　处：《Journal of Semiconductors》2013年第8期155-161,共7页半导体学报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China(No.SS2013AA011203);the Specialized Research Fund for the Doctoral Program of Higher Education of China(No.20110002110058)

摘　　要：A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.

关 键 词：DAC current-steering SFDR wide-band time-interleaved 

分 类 号：TN792[电子电信—电路与系统]