两级相干累加伪码捕获算法的FPGA实现  

FPGA Realization of PN Code Acquisition Algorithm Based on Two-stage Coherent Accumulation Method

作　　者：邓强[1] 

机构地区：[1]中国西南电子技术研究所,成都610036

出　　处：《电讯技术》2013年第8期1044-1048,共5页Telecommunication Engineering

摘　　要：针对现场可编程门阵列(FPGA)实现的伪码捕获算法中存在逻辑资源消耗大、频率估计精度差、判决门限计算复杂等问题,首先提出利用直接II型匹配滤波器结构实现第一级相关运算,做到逻辑资源与计算时间之间的平衡;然后提出利用线性调频Z变换(CZT)代替离散傅里叶变换(DFT)实现第二级相干累加,提高了频率估计精度并减小了频谱泄露;最后通过对判决量进行统计分析,给出了判决门限的自适应设置方法,并验证了其有效性。Aiming at the problem of large logic resource usage,poor frequency estimation and complicated decision threshold computation in implementing PN code acquisition method based on FPGA,the first-stage coherent accumulation using the Direct Form II matched filter is proposed,which can achieve the balance between the logic resource usage and the computation times.And then the second-stage coherent accumulation using CZT instead of DFT is proposed,which can improve frequency estimation precision and reduce frequency leakage.Finally,according to analysis of the statistical property of the decision variable,the adaptive setting method of decision threshold is given,and its effectiveness is verified.

关 键 词：直接序列扩频 伪码捕获 相干累加 捕获门限 自适应估计 

分 类 号：TN914.42[电子电信—通信与信息系统]