An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement  

作　　者：陈宏铭 郝跃国 赵龙 程玉华 

机构地区：[1]Shanghai Research Institute of Microelectronics(SHRIME), Peking University [2]School of Information Science and Technology,Peking University

出　　处：《Journal of Semiconductors》2013年第9期164-170,共7页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.60736030);the Research Program of Science and Technology Commission of Shanghai(No.11110707100);the National 02 Key Special Program of China(No.2009ZX02305-005)

摘　　要：An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measure- ment in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer （TIQ）-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capaci- tance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measure- ment in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer （TIQ）-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capaci- tance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.

关 键 词：successive approximation register analog-to-digital converter charge redistribution threshold in-verter quantizer 

分 类 号：TN958[电子电信—信号与信息处理] TN792[电子电信—信息与通信工程]