数字解码器的千兆网传输控制设计与实现  

Design and implementation of gigabit ethernet transmission controller on the digital decoder

作　　者：宁欣 刁鸣[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001

出　　处：《应用科技》2013年第4期38-41,共4页Applied Science and Technology

摘　　要：海量音视频信号的网络传输对系统通信的可靠性和稳定性提出更高的要求.针对该问题,提出FPGA配置千兆以太网控制芯片AX88180的硬件实现方案.通过Verilog HDL语言分模块实现网络传输系统的各个功能.设计了初始化模块,令AX88180与88E1111建立RGMII通信模式;然后设计了数据接收和发送模块,对UDP、ARP、ICMP和IGMP协议进行解封装和封装,为数据链路层和应用层提供中间连接.通过网络抓包工具Ethereal监测实时数据,验证系统良好的网络连接状况;使用数字解码器的软件功能统计传输速率和丢包率,验证此系统的通信速率符合MEPG-2标准,丢包率满足流媒体通信标准.The network transmission of mass audio and video signals makes higher demand on reliability and stability in the system communication. To meet this requirement, the hardware implementation scheme of FPGA configuring the gigabit ethernet controller chip AX88180 is proposed. The scheme achieves the various functions of the network transmission system by using the language sub-module Verilog HDL. The initialization module is designed first, establishing RGMII communication mode between AX88180 and 88El111, then data receiving and sending modules are designed to encapsulate and capsulate the protocols of UDP, ARP, ICMP, and IGMP, providing intermediate connection between data link layer and application layer. The monitoring of the real-time data during IRD by the network packet sniffing tool-Ethereal proved good network connectivity. Transmission rate and packet loss rate are counted by digital decoder software, verifying this communication rate is consistent with MEPG-2 standard, and the packet loss rate can meet the streaming media communication standards.

关 键 词：数字解码器 FPGA 网络传输 UDP IP协议 

分 类 号：TN914.34[电子电信—通信与信息系统]