一种适用于QPSK遥测接收机的符号定时估计器的FPGA实现研究  

A Simple FPGA Implementation Structure of Symbol Timing Estimator for QPSK Demodulation of Telemetry Receiver

作　　者：向东游 张华栋[1] 李忠亮[1] 

机构地区：[1]北京机电工程研究所,北京100074

出　　处：《计算机测量与控制》2013年第9期2538-2540,共3页Computer Measurement &Control

摘　　要：接收机是遥测系统的关键部件;针对全数字接收机,回顾和比较了几种传统非数据辅助定时估计算法,总结了不同算法的优劣和应用场合;针对遥测数字接收机中的QPSK解调器的符号同步环节,提出了一种易于FPGA实现的定时估计结构;通过计算机仿真和硬件实现表明,与传统定时估计器实现相比,该结构在保证估计性能和速度的前提下降低了设计复杂度,节省了硬件乘法器和片上ROM等重要逻辑资源,在遥测数字接收机的设计中具有一定实用价值。Receiver is the key component o{ telemetry, several non--data--aided feed--forward symbol timing estimating algorithms was reviewed and introduced of advantages and disadvantages. For symbol synchronization of QPSK signals, a simple FPGA implementation structure was introduced. Simulations and tests proved that compared with implementation of other conventional symbol timing estimator, the implementation complexity was reduced and logic resources saved.

关 键 词：遥测 接收机 符号同步 定时估计 

分 类 号：TN929.5[电子电信—通信与信息系统]