A novel ESD power supply clamp circuit with double pull-down paths  

作　　者：LIU HongXia YANG ZhaoNian LI Li ZHUO QingQing 

机构地区：[1]Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics, Xidian University

出　　处：《Science China(Information Sciences)》2013年第10期172-179,共8页中国科学（信息科学）（英文版）

基　　金：supported in part by National Natural Science Foundation of China(Grant Nos.60976068,60936005);Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program(Grant No.708083)

摘　　要：Electrostatic-discharge （ESD） protection design is one of the key challenges of advanced CMOS processes. RC-triggered and MOSFET-based power supply ESD clamp circuits have been widely used to ob- tain the desired ESD protection ability. In this paper, a MOSFET-based ESD power clamp circuit with only 10 ns RC time constant for 0.18-p^m process is presented. A double pull-down path is proposed to avoid false triggering, reject power supply noise and reduce energy consumption. The performance of the novel clamp circuit is excellent, consuming very small layout area. The simulation results show that this clamp circuit can be used in industry.Electrostatic-discharge （ESD） protection design is one of the key challenges of advanced CMOS processes. RC-triggered and MOSFET-based power supply ESD clamp circuits have been widely used to ob- tain the desired ESD protection ability. In this paper, a MOSFET-based ESD power clamp circuit with only 10 ns RC time constant for 0.18-p^m process is presented. A double pull-down path is proposed to avoid false triggering, reject power supply noise and reduce energy consumption. The performance of the novel clamp circuit is excellent, consuming very small layout area. The simulation results show that this clamp circuit can be used in industry.

关 键 词：ESD （electrostatic-discharge） clamp circuit DURATION false triggering power supply noise 

分 类 号：TN386[电子电信—物理电子学]