一种电容阵列结构的10位8通道1MS/s逐次逼近AD转换器  

A Capacitor Array Structure 10-bit 8-channels 1-MS/s SAR ADC

作　　者：陈宏铭 许升睿 曾玉光 

机构地区：[1]智原科技,上海200233

出　　处：《中国集成电路》2013年第10期28-35,共8页China lntegrated Circuit

摘　　要：设计了一种用于多电源SoC的10位8通道1MS/s逐次逼近结构AD转换器。为提高ADC精度,DAC采用改进的分段电容阵列结构。为降低功耗,比较器使用了反相器阈值电压量化器,在模拟输入信号的量化过程中减少静态功耗产生。电平转换器将低电压数字逻辑信号提升为高电平模拟信号。采用UMC 55nm 1P6M数字CMOS工艺上流片验证设计。测试结果表明,当采样频率为1 MS/s、输入信号频率为10 kHz正弦信号情况下,该ADC模块在3.3 V模拟电源电压和1.0 V数字电源电压下,具有最大微分非线性为0.5LSB,最大积分非线性为1LSB。测得的SFDR为75 dB,有效分辨率ENOB为9.27位。A 10-bit 8-channel 1 MS/s successive approximation analog-to-digital converter （ ADC ） used for multi-supply SoC is implemented. In order to achieve high accuracy, the DAC is implemented by using an improved segment capacitor array structure, the comparator use TIQ （ Threshold Inverter Quantizer ） to reduce static power consumption. We also adopt voltage level shifter to convert different voltages. The ADC core is fabricated in UMC 55nm 1P6M CMOS process. Testing results show that the maximum DNL and INL are measured to be less than 0.5 LSB and 1 LSB respectively with a 3.3 V analog supply and a 1.0 V digital supply. With a 10 kHz input signal sampled at 1 MS/s, the SFDR and ENOB are measured to be 75 dB and 9.27 Bits respectively.

关 键 词：逐次逼近ADC 比较器 电平转换器 

分 类 号：TN792[电子电信—电路与系统]