一种任意抽取数字下变频器的设计  

Design of an Arbitrary Decimation DDC

作　　者：袁子乔[1] 刘翔[1] 

机构地区：[1]西安电子工程研究所,西安710100

出　　处：《火控雷达技术》2013年第3期66-69,共4页Fire Control Radar Technology

摘　　要：数字下变频(DDC)技术作为连接前端模数转换器件(ADC)与后端通用数字信号处理器件之间的纽带,在雷达信号处理中占据了核心地位。针对雷达不同模式下抽取率不同的情况,本文提出了一种任意抽取数字下变频芯片的设计,实现了不同抽取率时的乘法器资源复用,节约了乘法器资源,降低了系统功耗和系统的复杂度。该数字下变频芯片采用SMIC0.13μm工艺进行综合仿真,综合结果满足指标要求。Digital down-conversion （DDC） plays a very important role in radar signal processing as a link between analog-to-digital converter （ADC） at the front-end and general digital signal processor at the back-end. To different decimation in different radar operate mode, design of an arbitrary decimation DDC application specific integrated circuit （ASIC） is provided for implementation of multiplexing of multiplier source, therefore multiplier source is saved and system power consumption and complexity are both reduced. Synthesized simulation to this DDC chip by using SMIC 0. 13 μm technology indicated that its performance can meet specification requirements.

关 键 词：专用集成电路 CORDIC 数字下变频 

分 类 号：TN911.7[电子电信—通信与信息系统]