WCDMA系统上行扰码算法的优化及其实现  

Optimization and its implementation of algorithm in WCDMA system uplink scramble

作　　者：陈高峰[1] 洪琪[1] 余鹏[1] 翟培苓[1] 

机构地区：[1]安徽大学电子信息工程学院,安徽合肥230601

出　　处：《安徽大学学报（自然科学版）》2013年第5期66-72,共7页Journal of Anhui University(Natural Science Edition)

基　　金：863计划资助项目(2009AA012201);专用集成电路与系统国家重点实验室开放基金资助项目(10KF014);安徽大学全日制研究生学术创新研究强化基金资助项目

摘　　要：针对WCDMA系统上行扰码中信号处理能力弱的问题,提出一种将1位串行输出电路转化为8位并行输出电路的算法,并与1位串行输出、2位并行输出和4位并行输出在资源面积、处理速度等方面进行比较,数据比较表明8位并行输出电路可以显著提高系统的信号处理能力.通过与文献(王文焕.用FPGA实现WCDMA下行扰码[J].现代电子技术.2002(2):62-63)在硬件及软件仿真两个方面的对比发现,该文算法的处理速度提高到原来的8倍.使用FPGA板实现该算法的硬件电路,且对此电路进行测试,结果表明该电路可以实现预期功能.In accordance with the problem that the signal processing ability of the uplink scrambling code was weak in WCDMA system, the paper proposed an algorithm, which translated 1 bit signal circuit into 8 bit parallel circuit in the uplink. Compared with others in area and processing speed, the algorithm of the 8 bit parallel circuit enhanced the capability of processing signal. Compared with original literature （Wang W H. Realization of WCDMA downlink scrambling code with the FPGA [ J]. Modern Electronics Technique, 2002（2） ：62-63） in synthesis of hardware and simulation, the speed of this algorithm increased to 8 times. Finally, the hardware structure was realized by field programmable gate array, and the test results showed that the circuit could realize the expected function.

关 键 词：WCDMA系统 上行扰码 串并转换 实现电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]