基于可编程逻辑器件的微型加速度存储测试仪  

Micro-acceleration Storage Tester Based on CPLD

作　　者：李婉蓉[1] 范锦彪[1] 王燕[1] 许其容[1] 

机构地区：[1]中北大学,山西太原030051

出　　处：《山西电子技术》2013年第5期3-4,11,共3页Shanxi Electronic Technology

摘　　要：在武器的研制过程中,引信、内外弹道、抗冲击性等都需要通过微型加速度存储测试仪进行测试。但测试环境比较恶劣,内载测试仪预留空间较小,g值较高。为了提高测试系统的灵活性和可靠性,提出了一种基于可编程逻辑器件CPLD的微型加速度测量系统,并具体阐述了该系统总体方案的设计思路及关键技术(利用CPLD内部丰富的逻辑单元实现了可高速采样,可防止误上电、可实现采样频率和负延迟可选等)。该系统在多次实际试验中得到了很好的应用。In the process of weapon development, all of fuse, internal ballistics, external ballistics and impact resistance should be tested through micro-acceleration tester. But when the test environment is relatively poor, the reserved space of containing tester is smaller, and the value of g will be higher. In order to improve the flexibility and reliability of the test system, the micro - acceleration measurement system based on programmable logic device is proposed, and the details of design ideas of the overall program and key technologies are expounded. The key technologies include ： with the rich internal logic unit of CPLD to achieve a high-speed sampling, to prevent inadvertent energization, to get sampling frequency and negative delay selection. A number of practical tests have shown that the system has very good application.

关 键 词：存储测试 加速度 复杂可编程逻辑器件(CPLD) 

分 类 号：TB934[一般工业技术—计量学] TP27[机械工程—测试计量技术及仪器]