基于FPGA的数字存储示波器对外围芯片的控制设计  

The Controlling Design of Digital Storage Oscilloscope to the Peripheral Chip Based on FPGA

作　　者：林盛鑫[1] 钟惠球[2] 黄丁香[3] 

机构地区：[1]东莞理工学院电子工程学院,广东东莞523808 [2]东莞理工学院资产后勤管理处,广东东莞523808 [3]东莞理工学院学报编辑部,广东东莞523808

出　　处：《东莞理工学院学报》2013年第5期20-26,共7页Journal of Dongguan University of Technology

摘　　要：数字存储示波器采用ARM与FPGA双处理器结合的嵌入式系统设计方案,重点介绍在FPGA中如何实现对外围芯片的通信与驱动,采用VHDL语言,以逐层描述的设计模式,分成ARM接口通信控制模块和外围芯片驱动功能模块,整个设计主要负责接收ARM的控制指令,根据其指令要求,发送控制命令到其它芯片驱动功能模块,协调整个数据采样过程,确保数据按照如采样率、采样方式、触发方式等参数设置要求进行采样,确保采样数据的可靠性。The Digital storage oscilloscope uses an embedded design system of ARM and FPGA dual -processor, focusing on how to achieve communication and drive for Peripheral chips in the FPGA .Using VHDL language and layer -by-layer descrip-tion of the design mode , this design is divided into ARM Interface communication control module and Peripheral chip driver function module, in charge of receiving ARM control instruction .According to their instructions , this device sends control commands to other chip-driven functional modules , coordinating the entire data sampling process and ensuring data in accordance with parameters , such as the sampling rate , sampling mode and trigger mode , as well as the reliability of sampling data .

关 键 词：数字存储示波器 可编程逻辑器件 超高速集成电路硬件描述语言 

分 类 号：TN914[电子电信—通信与信息系统]