无相位截断误差DDS的设计与FPGA实现  

Design and Implementation of Direct Digital Snthesizer without Phase Trunction Error Based on FPGA

作　　者：向伟[1] 沈诗律[2] 查智[1] 耿文豹[1] 

机构地区：[1]中国船舶重工集团公司710研究所 [2]西北工业大学电子信息学院

出　　处：《微型电脑应用》2013年第10期1-4,共4页Microcomputer Applications

基　　金：国家863高技术研究发展计划资助项目(NO.2012AA090901-05)

摘　　要：通过修改传统的直接数字频率合成(DDS)设计方法,提出了一种基于查找表的无相位截断误差的DDS设计方案并用FPGA平台予以实现。该方案不做相位截断,并利用幅度量化的数学特性建立查找表,在查找表深度可容忍的前提下大幅降低了杂散噪声,减轻了存储量对提高信号精度的限制,消除了传统设计中相位截断给最终输出信号频谱的影响,提高了DDS的性能。By modifying the traditional Direct Digital Synthesizer （DDS） design method, a novel solution without phase truncation error based on lookup table is introduced and implemented on FPGA platform in this paper. The solution take advantage of the am- plitude quantization the mathematical properties, spurious noise is significantly reduced in the lookup table depth tolerable premise, reduces the amount of storage constraints to improve the accuracy of the signal, eliminates the traditional design phase truncation to the final output signal spectrum, improves the performance of the DDS.

关 键 词：直接数字频率合成 查找表 相位截断误差 

分 类 号：TN741[电子电信—电路与系统]