一种降低高性能SRAM过大位线漏电流的方法  

A New Technique to Reduce Excessive Leakage Current on Bitline in High-Performance SRAM

作　　者：刘其龙[1] 丁夏夏[1] 李瑞兴[1] 吴秀龙[1] 谭守标[1] 

机构地区：[1]安徽大学电子信息工程学院,合肥230601

出　　处：《微电子学》2013年第4期494-498,共5页Microelectronics

基　　金：国家核高基资助项目(2011ZX01034-001-002-003)

摘　　要：随着半导体工艺的进步,器件特征尺寸不断缩小,晶体管漏电流呈现出增长趋势。高速SRAM位线上,过大的漏电流会引起SRAM的性能出现严重下降,甚至导致SRAM读失效的发生。特别是当位线上积累的漏电流已经超过SRAM的工作电流时,传统方法将趋于失效。提出位线自截断技术来消除过大漏电流对SRAM的不利影响。采用SMIC 65nm CMOS工艺,设计了一款SRAM,通过仿真测试,验证了该方法的正确性。With ever shrinking feature size due to the progress of semiconductor process, leakage current o＊ transistor is becoming larger. Excessive leakage current on bitline in high speed SRAM may cause severe performance degradation, even leading to read failure of SRAM. Particularly, when the accumulated bitline leakage current exceeds operating current of SRAM in the worst case, conventional techniques tend to malfunction. A so- called bitline self cut-off technique was proposed to cancel the effects of excessive bitline leakage current on the performance of SRAM. An SRAM was designed based on SMIC＇ s 65 nm CMOS process to verify the method. Simulation and test results were in good agreement, which validated the new technique.

关 键 词：SRAM 位线漏电流 漏电流降低 位线自截断 

分 类 号：TN492[电子电信—微电子学与固体电子学]