连续相位调制解调器的FPGA实现  

Implementation of CPM Modem Based on FPGA

作　　者：赵旦峰[1] 马立坤[1] 周相超[1] 高敬鹏[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,哈尔滨150001

出　　处：《微电子学》2013年第5期641-645,共5页Microelectronics

基　　金："十一.五"国防预研基金资助项目(xxxx607010102)

摘　　要：针对连续相位调制解调硬件实现复杂度高的问题,提出一种基于FPGA的低复杂度硬件实现方案。该方案中,调制器采用查表法,解调器采用Max-Log-MAP算法。该方案具有复杂度低、速度快、易于生成IP核等优点。利用Xilinx公司的Virtex-2Pro系列开发板,对调制解调器进行测试,验证了该系统方案的正确性。该设计可作为连续相位调制解调专用集成芯片开发的参考。In view of the high complexity in hardware implementation of the continuous phase modem, a hardware implementation scheme based on FPGA was proposed, in which look-up table method and Max-Log-MAP algorithm were used for modulator and demodulator, respectively. The scheme featured low complexity, high speed and easy generation of IP core. The modem was tested based on Virtex-2 Pro series development board of Xilinx. Test results validated the proposed scheme The design could be used as a reference for development of continuous phase modem IC.

关 键 词：连续相位调制 MAX-LOG-MAP算法 查表法 FPGA 

分 类 号：TN76[电子电信—电路与系统]