嵌入式I^2C从机设计验证与版图实现  

Design Verification and Implementation of Embedded I2C Slave Circuit

作　　者：聂拓[1] 谢亮[1] 曾以成[1] 刘杨[1] 金湘亮[1] 

机构地区：[1]湘潭大学材料与光电物理学院,湖南湘潭411105

出　　处：《微电子学》2013年第5期674-678,共5页Microelectronics

基　　金：中国科学技术部国家重大科技项目(20112x05008-005-04-02);国家自然科学基金资助项目(60972147);湖南省自然科学基金资助项目(12JJ4064)

摘　　要：提出了一种嵌入式标准化I2C从机设计方案,对传统I2 C从机的状态机进行简化,得到了改进型状态机。综合结果表明,与传统状态机相比,改进型状态机的面积减少约20%,功耗降低约4%。以一款芯片为例,详细介绍了I2 C总线嵌入式开发过程。该方案已通过功能仿真、FPGA验证及版图后仿真。对该电路进行FPGA验证,构建了一种简单、高效的FPGA验证系统。An embedded standardized I^2C slave circuit was presented. Traditional state machine for slave I^2C bus was simplified, and a modified state machine was obtained. Synthesis results showed that the modified state machine had an area reduction of about 20% and power reduction of about 4%, compared with traditional state machine. With a chip as an example, development process of I^2C bus embedment was described in detail. The circuit design passed behavioral simulation, FPGA verification and post-layout timing simulation. Finally, an easy and efficient method for FPGA verification was constructed to validate the circuit.

关 键 词：I2C从机 嵌入式系统 状态机 现场可编程门阵列 

分 类 号：TN432[电子电信—微电子学与固体电子学]