相位噪声测量在时钟偏斜测试中的应用  

Application of Phase Noise Measurement to Clock Skew Testing

作　　者：王小强[1] 

机构地区：[1]工业和信息化部电子第五研究所,广州510610

出　　处：《微电子学》2013年第5期713-715,726,共4页Microelectronics

摘　　要：随着系统数据速率的提高,时钟抖动分析的需求也在与日俱增。在高速数据链路中,时钟分配器的时钟偏斜会影响系统的整体性能。分析了相位噪声和时钟抖动的对应关系,通过时域到频域的转换,实现了时钟偏斜参数的高精度测量。以一款时钟分配器为例,进行了实际测试验证。With boosting system data-rate, demand for clock jitter analysis is ever increasing. In high speed digital link, clock skew of the clock distributor may have some effects on performance of the system. Relationship between phase noise and clock jitter was analyzed, and high precision measurement of skew parameter was achieved by transformation from time domain to frequency domain. With a clock distributor as an example, an actual measurement was made to verify the effectiveness of the method.

关 键 词：时钟偏斜 相位噪声 时钟抖动 

分 类 号：TN911.4[电子电信—通信与信息系统]