一种并行的定时同步环路实现研究  

A Novel Interpolator Controlling Scheme in High-Speed Digital Timing Recovery Loop

作　　者：刘旺[1] 朱江[1] 付永明[1] 郄志鹏[1] 

机构地区：[1]国防科学技术大学电子科学与工程学院,湖南长沙410073

出　　处：《通信技术》2013年第10期1-5,共5页Communications Technology

摘　　要：定时恢复是全数字接收机中的核心部分之一,其处理速度制约了整个接收机的最高处理速度。在传统Gardner定时环路的实现基础上,提出了一种适用于高速数字接收机中定时同步环路的并行控制方式。它通过采用并行处理的方法,为符号同步环路中的内插滤波器提供插值相位来实现插值功能,并且降低了定时同步环路的工作时钟。MATLAB仿真证明这种插值滤波控制器在降低定时同步环路工作时钟频率的同时,定时恢复性能并未受到影响。Timing recovery is one of the core parts for full-digital receivers, its processing speed is a re- straint to the maximum processing speed of the receiver. Based on conventional Gardner timing recovery, a modified timing recovery method involved a parallel controller in the high speed digital receivers is pro- posed. The modified controller can be used to provide interpolated phase for the interpolator to realize the interpolation function and decrease the system＇ s sampling clock via parallel scheme at the same time. With 8psk signals as an example, this configuration is simulated and verified, indicating that the proposed inter- polator controller is a good solution to timing recovery, and effective for increasing data rate in timing loop, and thus can be used to implement fairly high incoming data.

关 键 词：Gardner定时 内插控制器 并行结构 

分 类 号：TN919.6[电子电信—通信与信息系统]