A 4 GHz 32 bit direct digital frequency synthesizer based on a novel architecture  

作　　者：武锦 陈建武 吴旦昱 周磊 江帆 金智 刘新宇 

机构地区：[1]Institute of Microelectronics, Chinese Academy of Sciences [2]Key Laboratory of Microelectronics Devices & Integrated Technology

出　　处：《Journal of Semiconductors》2013年第11期136-141,共6页半导体学报（英文版）

基　　金：supported by the National Basic Research Program of China(No.2010CB327505)

摘　　要：This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.

关 键 词：direct digital frequency synthesis read-only memory digital-to-analog converter gallium arsenide heterojunction bipolar transistor 

分 类 号：TN741[电子电信—电路与系统] TP332[自动化与计算机技术—计算机系统结构]