采用新型低成本共模反馈电路的全差分运放设计  

Design of fully differential operational amplifier with low cost common feedback circuit

作　　者：雷鑑铭[1] 胡北稳 桂涵姝 张乐[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《浙江大学学报（工学版）》2013年第10期1777-1783,共7页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(60706003)

摘　　要：设计应用于流水线型ADC的全差分运算放大器.运放中共模反馈电路采用调节反馈深度和共用差分信号通路的新型结构来实现,用简单的结构实现了高环路增益,通过降低反馈系数的方法防止电路产生自激振荡,避免了因引用补偿电容带来的高成本和高设计难度.放大器采用两级折叠共源共栅结构并进行频率补偿,输出级采用推挽式AB类结构.设计的全差分运算放大器基于中芯国际(SMIC)0.35μm工艺.后仿结果表明,放大器直流增益为100dB,负载为3pF时单位增益带宽为359MHz,相位裕度为68°,建立时间为12.3ns,满足ADC所要求的性能指标,适用于高精度流水线型ADC中的级间增益电路和采样保持电路.A fully differential operational amplifier （AMP） for pipelined ADC was designed. A simple common mode feedback （CMFB） structure by adjusting the feedback quantity and sharing the differential signal path was proposed to improve the loop gain. The auto-oscillation of the circuit was prevented by reducing the feedback coefficient, and the high design cost and high design difficulty caused by the application of the compensation capacitance were avoided. The amplifier contains a two-stage folded cascode architecture and is frequency compensated, and the output stage uses a push-pull elass-AB structure. The amplifier uses the SMIC 0.35 /~m technology. The post-layout simulation results show that the open gain is up to 100 dB, the unity gain bandwidth （UGB） is 359 MHz with a 3 pF load, the phase margin （PM） is 68~ and the settling time is 12.3 ns. All the specifications meet the design requirements of the ADC. This fully differential operational amplifier is appropriate to be used in the inter-stage gain circuit and the sample-hold circuit of high accuracy pipelined ADC.

关 键 词：流水线型ADC 全差分 共模反馈 折叠共源共栅结构 

分 类 号：TN432[电子电信—微电子学与固体电子学]